1. Field of the Invention
The present invention relates to semiconductor memory devices and more specifically to a configuration of a semiconductor memory device having a plurality of memory cell arrays distributed in arrangement and capable of operating the plurality of memory cell arrays consistently.
2. Description of the Background Art
Recently, as semiconductor memories have larger capacity, there has been the need to provide on one chip a plurality of memory circuits with the same function and operate the circuits consistently.
FIG. 26 is a block diagram showing as one example of such a memory device an entire configuration of a synchronous DRAM (SDRAM) capable of operating eight memory cell arrays having a same function consistently, shown as a conventional semiconductor memory device 100 in the figure.
Referring to FIG. 26, semiconductor memory device 100 is provided with a clock signal terminal 102, an address signal terminal 103, a control signal terminal 104, a data input/output terminal 106, a power supply terminal 108 and a ground potential terminal 109 as input/output terminals for signal communication with the external.
Semiconductor memory device 100 also includes buffer circuits 112-116 provided for signals communicated via input/output terminals, a control circuit 110, a memory cell array 150 and a sense amplifier (SA)-I/O circuit 151, a control signal bus 117 communicating a signal between control circuit 110 and SA-I/O circuit 151, and a data bus 118 for transmitting data between memory cell array 150 and input/output buffer 116.
Control circuit 110 responds to the clock, address and control signals externally applied via input/output terminals 102-104 to produce a control clock corresponding to a predetermined mode of operation and synchronizing with the signals to generally control the operation of semiconductor memory device 100. Control circuit 110 is commonly provided for the eight memory cell arrays and controls the operation of SA-I/O circuit 151 via control signal bus 117 to operate the memory cell arrays with the same function consistently.
However, since the conventional semiconductor memory device 100 has control circuit 110 provided commonly for all of the memory cell arrays, all of the signals required for controlling the operation of each memory cell array need be transmitted via control signal 131. This significantly increases the number of interconnections of control signal bus 117. Thus the load on the signal interconnections is increased and consequently the delay, distortion and the like of a signal is disadvantageously caused and chip area is disadvantageously increased.